High-performance full adder design based on SRPL

HAN Jin-liang; ZHANG Yue-jun; WEN Liang; ZHANG Hui-hong

doi:10.13374/j.issn2095-9389.2019.08.03.001

Volume 42 Issue 8

Aug. 2020

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Article Navigation > Chinese Journal of Engineering > 2020 > 42(8): 1065-1073

HAN Jin-liang, ZHANG Yue-jun, WEN Liang, ZHANG Hui-hong. High-performance full adder design based on SRPL[J]. Chinese Journal of Engineering, 2020, 42(8): 1065-1073. doi: 10.13374/j.issn2095-9389.2019.08.03.001

Citation:

HAN Jin-liang, ZHANG Yue-jun, WEN Liang, ZHANG Hui-hong. High-performance full adder design based on SRPL[J]. Chinese Journal of Engineering, 2020, 42(8): 1065-1073. doi: 10.13374/j.issn2095-9389.2019.08.03.001

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High-performance full adder design based on SRPL

doi: 10.13374/j.issn2095-9389.2019.08.03.001

1.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
2.
Department of Electronic Technology, China Coast Guard Academy, Ningbo 315211, China

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Corresponding author: E-mail: zhangyuejun@nbu.edu.cn
Received Date: 2019-08-03
Publish Date: 2020-09-11

Abstract

Abstract

The adder circuit is the core component of the high-performance system-on-chip (SoC). It is also important in image and voice encryption. The full adder circuit is a basic unit with a very high reuse rate among all the units. Therefore, the design of an adder with high energy efficiency is of great significance for the optimization of digital circuit systems. In recent years, numerous researchers have studied the design of advanced adder circuits, which are characterized by high speed and low power consumption. To reduce the hardware overhead, an increasing number of adder circuits utilize the transmission tube logic to reduce the number of transistors. However, this method also brings about several negative effects, such as threshold loss and performance degradation. In this paper, by studying the swing recovery logic and full adder circuit, we proposed a full adder design scheme based on swing restored pass-transistor logic (SRPL). First, the threshold loss mechanism of the circuit was analyzed, and the characteristics of the high-efficiency transmission of high-level and low-level transistors were considered; then the design method of the swing recovery transmission tube logic was developed. We used a symmetric structure to design an XOR/XNOR circuit without delay deviation output. The two-shot MOS tube was used to compensate the threshold loss to realize the full swing output of the XOR/XNOR circuit. Finally, we fused the designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum circuit and the improved transmission gate carry circuit to implement the high-performance full adder for swing recovery. In the TSMC 65 nm process, the logic function of our method was verified by HSPICE simulation. Compared with the conventional approach, the delay is reduced by 10.8%, and the power-delay product (PDP) is reduced by more than 13.5%. The design method of low delay and full swing output of the SRPL circuit can be further applied to the design of other logic circuits, further promoting the practical process of the SRPL circuit.
- XOR/XNOR circuit,
- swing recovery,
- high-performance full adder,
- threshold loss,
- full swing

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References(25)

References

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