High-speed network access technology based on DDR memory bus

In cluster, the performance of an interconnection network exhibits significant effect on that of the whole cluster system. The interconnection network is required to possess the characteristics of high bandwidth, low delay and high reliability. Traditional interconnection network access technologies are almost based on the peripheral component interface (PCI). This paper proposed a design ideology of access based on DDR DIMM interface and presented a design of the network interface on FPGA. The access bandwidth could be increased by reading and writing memory directly. Parts of the communication protocols were downloaded into the network interface card (NIC) to improve the parallel of calculation and communication. Measurements indicate that excluding the upper layer protocol, the access bandwidth of the NIC can reach to 3120 Mbps. An implementation approach of the NIC for FPGA was put forward and was simulated on an XC2VP20 FPGA chip of Xilinx Corporation.