VLIW Architecture Microprocessor Functional Verification Model

When the architecture and organization of microprocessor is becoming more and more complex, the problem about how to verify the microprocessor function is becoming more and more important. In order to design the functional verification stimulus of microprocessor effectively, a functional verification model of VLIW architectural processor is introduced, based on the organization characteristic, especially the parallel pipeline, in the VLIW microprocessor. Based on the verification model, a verification schema and 100,000 cycle of stimulus for a VLIW microprocessor design have been finished, which includes about 1500 Kbit gates.